![]() ![]() ![]() Applying analogy, we realise that when clock=1 the input to the CMOS pass transistor should be D and when clock=0 the input to the pass transistor should be value of D just before the transition of clock from 1 to 0.To obtain the value of D just before transition a buffer is needed.The final design is given below: As mentioned earlier, when the clock is high the input D propogates to the output Q as it is and when the clock is low the output is held(irrespective of the changes in input D).This definition indicates that D latch can be implemented as a multiplexer with clock signal as the select input of multiplexer. With the definition of D latch and D flip-flop(given in the introduction) and the background knowledge of pass transistor(accquired in the fourth experiment) let us design the transistor level diagram of D latch in this experiment.
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